Conventionally, a differential amplifier has been widely used as an operational amplifier circuit for its beneficial feature that a gain can be maintained constant without being affected by a change in a power source voltage or an ambient temperature if characteristics of the input transistor are uniform. The operational amplifier circuit is used not only as an amplifier but also constituting various circuits such as a voltage follower circuit, a differential integration circuit or a filter, etc.
As shown in FIG. 13, for example, in the arrangement where an operational amplifier circuit 101 is formed on a MOS (Metal Oxide Semiconductor) integrated circuit, the operational amplifier circuit 101 includes a differential input comparison circuit 102 for outputting a comparison current I.sub.CMP according to a difference between an non-inverting input voltage V.sub.IN1 and an inverting input voltage V.sub.IN2, and an output buffer circuit 103 for outputting an output voltage V.sub.OUT according to the comparison current I.sub.CMP. In an input circuit 104 of the differential input comparison circuit 102, an input transistor N111, i.e., an NMOS transistor, controls a current I.sub.1 that flows from a drain to a source in response to the non-inverting input V.sub.IN1 to be applied to a gate, and an input transistor N112 controls a current flowing therethrough according to the inverting input V.sub.IN2. To the respective sources of the input transistors N111 and N112 are mutually connected, a predetermined bias current is applied to through a drain of an N-type MOS transistor N103.
Furthermore, to the respective drains of the input transistors N111 and N112, the drains of the P-type MOS transistors P101 and P102 which constitute a current mirror circuit are respectively connected. Additionally, the gate and the drain of the MOS transistor P102 are mutually connected. As a result, the current mirror circuit is operated as an active load, and the MOS transistor P101 outputs a current in the same amount as a current I.sub.2 flowing through the input transistor N112 from its drain to the drain of the input transistor N111. On the other hand, as the input transistor N111 absorbs a current I.sub.1 in response to the non-inverting input V.sub.IN1, the comparison current I.sub.CMP according to the difference between the currents I.sub.2 and I.sub.1 is output from a junction of the MOS transistor P101 and the input transistor N111 to the output buffer circuit 103.
On the other hand, the comparison current I.sub.CMP is applied to a gate of the P-type MOS transistor P131 provided in the output buffer circuit 103. To the source of the MOS transistor P131, a power source voltage V.sub.cc is applied, and to the drain thereof, an N-type MOS transistor N132 is connected as a constant current source for determining a bias current of the output buffer circuit 103. As a result, from a junction between the MOS transistors P131 and N132, an output voltage V.sub.OUT according to the comparison current I.sub.CMP is output.
In the case of forming a voltage follower circuit of a negative feedback circuit by connecting an output terminal OUT of the operational amplifier circuit 101 to an inverting input terminal IN2, when the non-inverting input V.sub.IN1 is higher than the output voltage V.sub.OUT (inverting input V.sub.IN2) , in the differential input comparison circuit 102, the current I.sub.1 flowing in the input transistor N111 becomes greater than the current I.sub.2 flowing in the input transistor N112 and exceeds the current I.sub.2 to be transmitted to the input transistor N111 via the current mirror circuit composed of the MOS transistors P101 and P102. Therefore, a potential of the junction between the MOS transistors P101 and P102, i.e., a gate potential of the MOS transistor P131 is lowered, and a current flowing in the output buffer circuit 103 increases. As a result, the operational amplifier circuit 101 increases an output voltage V.sub.OUT (inverting input V.sub.IN2). On the other hand, in the case where a non-inverting input V.sub.IN1 is low, the current I.sub.1 flowing through the input transistor N111 becomes lower than the current I.sub.2 to be applied from the MOS transistor P101. As a result, in the output buffer circuit 103, a gate potential of the MOS transistor P131 increases, and a current flowing through the MOS transistor P131 decreases. On the other hand, as the MOS transistor N132 is the constant current source, it absorbs a current from the output terminal OUT and lowers the output voltage V.sub.OUT (inverting input V.sub.IN2).
Therefore, in the operational amplifier circuit 101, the output voltage V.sub.OUT (inverting input V.sub.IN2) increases or decreases so as to eliminate a potential difference from the non-inverting input V.sub.IN1, and the voltages V.sub.IN1 and V.sub.OUT finally become in the same potential. As a result, the operational amplifier circuit 101 can output the same voltage V.sub.OUT as the non-inverting input V.sub.IN1 by converting the impedance of the voltage signal V.sub.IN1 to be applied to the non-inverting input terminal IN1.
The operational amplifier circuit 101 having the described arrangement operates almost in the same manner even if the polarities of all the transistors inverse. In the following, like the operational amplifier circuit 101, a circuit having N-type input transistors is referred to as a N-channel simple input direction circuit, and like the operational amplifier circuit 111 shown in FIG. 14, a circuit having a P-channel input transistor is referred to as a P-channel simple input direction circuit. Additionally, the operational amplifier circuit 111 has the same arrangement as the operational amplifier circuit 101, except for that respective polarities of all the transistors, areas subjected to an application of the power source voltage V.sub.CC and GND inverse.
However, in each of the described arrangements, a range of a common input voltage V.sub.IN at which the operational amplifier circuit is operable, i.e., the input dynamic range of the operational amplifier circuit is restricted to be extremely narrow compared with the range of the power source voltage.
A concrete example will be given through an operational amplifier circuit 101 shown in FIG. 13. When the common input voltage V.sub.IN of the inputs V.sub.IN1 .multidot.V.sub.IN2 varies, a source potential of the input transistors N111 and N112 increases or decreases. Therefore, when the common input voltage V.sub.IN is lowered, the threshold value voltage V.sub.thN of the input transistors N111 and N112 may not be ensured. In this case, the input transistors N111 and N112 become inoperable, and the operational amplifier circuit 101 cannot output the output voltage V.sub.OUT according to a difference between the inputs V.sub.IN1 and V.sub.IN2. As a result, the input dynamic range of the operational amplifier circuit 101 becomes narrower by the threshold voltage V.sub.thN compared with the range of the power source voltage, and the operational amplifier circuit 101 cannot be operated in the case where the common input voltage V.sub.IN is in a range of GND&lt;V.sub.IN &lt;V.sub.thN. Similarly, the operational amplifier circuit 111 shown in FIG. 14 is arranged such that the input dynamic range becomes narrower by the threshold value voltage V.sub.thP of the input transistors P111 and P112. Therefore, when the common input voltage V.sub.IN increases to be fall in the range of .sub.VCC -V.sub.thP &lt;V.sub.IN &lt;V.sub.CC, an operational amplifier circuit 111 cannot be operated.
For example, in the case of forming each input transistor by the MOS of the enhancement type by a generally used IC manufacturing process, a threshold value voltage becomes around 1V, which cannot be ignored, especially in an operational amplifier circuit that can be operated at a low power source voltage. Therefore, irrespectively of a threshold value voltage of the input transistor, an operational amplifier circuit that can be operated in an entire range of from the GND potential to the power source voltage V.sub.CC is strongly demanded.
In the case of forming an input transistor by a transistor that can conduct when a voltage between a gate and a source is 0V, such as a depletion mode MOS transistor, etc., the operational amplifier circuit becomes operable in an entire region from the GND potential to the power source voltage V.sub.CC. However, in this case, a separate manufacturing process is required in addition to a normal IC manufacturing process, and it becomes difficult to manufacture a high operational amplifier circuit having a high integration.
On the other hand, Japanese Unexamined Patent Publication No. 92008/1990 (Tokukaihei 2-92008) discloses an operational amplifier circuit which is driven bi-directionally as an arrangement which can be manufactured by the normal IC manufacturing process and permits a wide input dynamic range. As shown in FIG. 15, an operational amplifier circuit 121 includes a differential input comparison circuit 122a for outputting a comparison current I.sub.CMPb having the same arrangement as the differential input comparison circuit 112 shown in FIG. 14, and an output buffer circuit 123 for generating an output voltage V.sub.OUT based on the comparison currents I.sub.CMPa and I.sub.CMPb.
The output buffer circuit 123 has the P-type MOS transistor P131 and the N-type MOS transistor N131 whose drains are respectively connected. The source of the MOS transistor P131 is connected to the power source voltage V.sub.CC, and the source of the MOS transistor P131 is connected to ground. To the respective gates of the MOS transistors P131 and N131, the comparison currents I.sub.CMPa .multidot.I.sub.CMPb are supplied. As a result, the output buffer circuit 123 synthesizes the comparison currents I.sub.CMPa .multidot.I.sub.CMPb of the differential input comparison circuits 122a and 112b by the push-pull system and the source ground system, and outputs an output voltage V.sub.OUT. 15. In the described arrangement, the differential input comparison circuits 122a and 122b operate in the range where the common input voltage V.sub.IN of the inputs V.sub.IN1 and V.sub.IN2 satisfy the range of V.sub.thN &lt;V.sub.IN &lt;V.sub.cc -V.sub.thP. On the other hand, in the range of GND&lt;V.sub.IN &lt;V.sub.thN, only the differential input comparison circuit 122b operates, an d in a range of V.sub.cc -V.sub.thP &lt;V.sub.IN &lt;V.sub.cc, only the differential input comparison circuit 122a operates. In the case where one of the differential input comparison circuits 122a and 122b is not operated, between the MOS transistor P131 and the N131 which constitute the output buffer circuit 123, the MOS transistor connected to the differential input comparison circuits 122a and 122b is operated as the other constant current load. Then, the input dynamic range of the operational amplifier circuit 121 is expanded to an entire range of the power source voltage V.sub.CC.
However, according to the operational amplifier circuit 121, in the output buffer circuit 123, the high level of the output voltage V.sub.OUT is restricted by the operable range of the MOS transistor P131, and the low level of the output voltage V.sub.OUT is restricted by the operable region of the MOS transistor N131. As a result, a new problem is raised in that the output dynamic range of the operational amplifier circuit 121 becomes narrower.
Especially, in the case of forming the voltage follower circuit of a negative feed back circuit by connecting the output terminal OUT and the inverting input terminal IN2 of the operational amplifier 121, a reduction in an output dynamic range directly causes an input dynamic range to be reduced. Therefore, the operational amplifier circuit 121 does not enable a significant increase in an input dynamic range.